ram-reg

module simple_ram(data,write_address,read_address,clk,we,out);

input[7:0] data;
input[3:0] read_address,write_address;
input we,clk;
output out;

reg[7:0] out;

reg[7:0] simpleram[15:0];

always@(posedge clk)
begin

if(we)
simpleram[write_address] <= data;



out<= simpleram[read_address];
end
endmodule

module simple_ram_tst;

reg[3:0] read_address, write_address;

reg clk, we;

reg[7:0] data;

wire[7:0] out;

simple_ram s1(data,write_address,read_address,clk,we,out);

initial
begin

clk=1'b0;we=1'b0;

#5 we=1'b1; data=8'd128;
write_address=4'd10;
#5 data=8'd4;
write_address=4'd2;
#50 read_address=4'd2;
#50 read_address=4'd10;
#500 $finish;

end

always #3 clk=~clk;

endmodule

module top (clk, rw, rdy, oe, we);
input clk;
reg y1=0, y2=0;
input rw, rdy;
output reg oe=0, we=0;

always @ (posedge clk) begin
case ({y1,y2,rw,rdy})
4'b0000: {y1,y2,oe,we} <= 4'b0000;
4'b0001: {y1,y2,oe,we} <= 4'b0100;
4'b0011: {y1,y2,oe,we} <= 4'b0100;
4'b0010: {y1,y2,oe,we} <= 4'b0000;
4'b0100: {y1,y2,oe,we} <= 4'b1100;
4'b0101: {y1,y2,oe,we} <= 4'b1100;
4'b0111: {y1,y2,oe,we} <= 4'b1000;
4'b0110: {y1,y2,oe,we} <= 4'b1000;
4'b1100: {y1,y2,oe,we} <= 4'b1101;
4'b1101: {y1,y2,oe,we} <= 4'b0001;
4'b1111: {y1,y2,oe,we} <= 4'b0001;
4'b1110: {y1,y2,oe,we} <= 4'b1101;
4'b1000: {y1,y2,oe,we} <= 4'b1010;
4'b1001: {y1,y2,oe,we} <= 4'b0010;
4'b1011: {y1,y2,oe,we} <= 4'b0010;
4'b1010: {y1,y2,oe,we} <= 4'b1010;
endcase
end
endmodule







--
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